In the reliability engineering of integrated circuits, it is necessary to predict product lifetimes and calculate defect densities. To accomplish this in a short time, it is necessary to subject product samples to environmental conditions that accelerate the failure modes that cause wearout. Typical methods for creating these stress conditions include the use of temperature and voltage such that the stress temperature used for testing exceeds the operating temperature when the circuit is in actual use, and such that the stress voltage used for testing exceeds the operating voltage when the circuit is in actual use.
Voltage acceleration has been used as the primary factor for gate and node dielectric stressing throughout CMOS history. An example of voltage stressing of a memory array is described below with reference to FIGS. 1 through 6.
FIG. 1 illustrates a typical memory array 8 with intersecting word lines 10 and bit lines 12. Referring now to FIG. 2, a three-dimensional plan view of the typical memory array 8 of FIG. 1, in this case a DRAM, is illustrated. Typical DRAMs are known in the art, thus only briefly discussed herein. The DRAM 8 includes intersecting word lines 10 and bit lines 12. Each bit line 12 is connected to a diffusion 14 by way of a via, or contact 16. This connection is shown in greater detail in the enlarged portion of memory array 8, shown in FIG. 3. For simplicity, dielectric material 15 has been omitted except as shown in the enlarged portion of FIG. 3. The DRAM 8 shown uses trench capacitors 18 as the storage elements. However, stack capacitors are also widely used.
Voltage stressing for integrated circuits is known in the art. FIG. 4 depicts a known testing method where all the word lines 10 and bit lines 12 of a test structure are connected together to allow for voltage stressing of all of the gate or node dielectric structures of memory array 8 at the same time. (It is assumed that the substrate is grounded). The portion of the gate dielectric stressed during reliability testing is shown by the dashed line 17 in the enlarged portion of FIG. 3. The node dielectric, i.e., the dielectric (not shown) separating node 18 from the surrounding silicon, is also stressed.
During a voltage stressing of a gate dielectric or of a node 18, a desired word line 10 is activated (i.e. a voltage potential is applied to the word line 10) for turning on an associated field effect transistor (FET) 31 (shown in FIG. 5). As shown in FIG. 5, the associated bit line 20 is thus connected, through connection 30, with a corresponding storage node 18. As discussed below, the voltage potential applied to the bit line is at most twice the use voltage, Vuse. Voltage stressing in this manner stresses both the gate dielectric 17 and the node dielectric (not shown) associated with node 18, or, if no bias is applied to bit line 20, just gate dielectric 17 is stressed. The gate dielectric 17 is also shown (by a dashed line) in FIG. 6, which depicts a side view of FET 31. Of course, either nFETs or pFETs can be used as the array transfer devices.
As operating voltages decrease and the gate dielectrics and junctions get thinner, however, significant voltage acceleration has become more difficult to achieve. One frequently used voltage acceleration model expresses the voltage acceleration by the formula Vacc=e.sup..beta.(Vstress-Vuse). In this formula, .beta. is constant. The acceleration thus is dependent on the voltage difference. However, the junctions/circuits typically can only tolerate a stress voltage, Vstress, of at most twice the use voltage, Vuse. For a 5 volt technology the stress-to-use difference is 10 volts minus 5 volts, resulting in 5 volts, but for a 2.5 volt technology the stress-to-use difference is only 5 volts minus 2.5 volts, resulting in 2.5 volts. Since this difference (Vstress-Vuse)is then raised to a power, the maximum resultant voltage acceleration is significantly reduced. As integrated circuit dimensions continue to decrease, and become ever smaller, this decreasing voltage trend will continue. A use voltage of 1.8 V is already on the horizon. Hence this limitation on voltage acceleration is a very significant new constraint.
During the stressing of gate or node dielectrics, the temperatures normally are limited to 200.degree. C. Wafer probing at higher wafer temperatures typically results in the probes moving slightly and causing damage to the chip. Module stressing can utilize somewhat higher temperatures, but also is limited because of the melting point of the normal chip mount metallurgies. Although special actions can be taken for short term wafer stressing up to 300.degree. C., and special actions can permit module stressing up to at least 300.degree. C., these activities require more expensive equipment and additional experimental time and precautions.
The normal use temperature of a chip is often at least 100.degree. C. If that chip is stressed at 200.degree. C., little temperature acceleration can be achieved. The typical model used for temperature stressing is an Arhennius model of the form Tacc=e.sup..DELTA.Hik.DELTA.T where .DELTA.T=(Tuse-Tstress) Kelvin, k is Boltzman's constant and .DELTA.H is a constant.
If stressing could be done at higher temperatures, the acceleration would be larger, depending on the value of .DELTA.H which typically is between 0.3 and 0.7. This could provide the necessary acceleration to establish the gate and node dielectric reliability for the next several generations.
Given the above-described constraints on voltage differentials and temperature differentials, the problem is how to simply achieve a reasonable acceleration when doing reliability stressing of thin gate and node dielectrics for low voltage technologies.